Application Notes

Clocking the FPGA

FPGA/Host Register Synchronization

Thus there is a need for synchronization between the local bus logics in LCLK domain and the user logics in the UCLK domain. This interface is presented as a 32-entry array of 64-bit registers. This notes presents the synchronization scheme of this register interface. The frequency of UCLK is assumed to be faster than that of LCLK.

FPGA/Host FIFO Interface Problems

Access External Memory from FPGA

FIFO Interface in FPGA for External Memory