FPGA/Host interface using FIFO
------------------------------

There are difficulties of using a FIFO to interface the host computer and
the ADM-XRC-5T2 FPGA board.

In the HDL template in AXEL SDK, the interface between host and FPGA is
based on a set of registers mapped to host memory space. The actual
implementation of the registers is in the FPGA design. It is intuitive
to instantiate a FIFO in the FPGA and connect the input or the output of
it to the register port. This straight forward implementation may cause
problems such as reading same data multiple times. This is caused by the
asynchronous nature of the interface. The problem is detailed below.

The host interface uses the local bus clock, lclk, and the FPGA circuit
use the memory clock, mclk. Synchronization is done by the
"user_reg_sync" and "reg_sync" components in the SDK library. In the
reg_sync component, the output of the FIFO is registered by the mclk
first and then by the lclk before going to the host. The enable signals
of this two registers are created by a ring of registers.  Half of the
ring, 3 registers, is clocked by mclk and the other half, 4 registers,
is clocked by lclk. There is an inverter in the ring. This structure
will generate the enable signals periodically the makes sure that two
signals are synchronous to their own clock domain without overlapping on
each other. Thus the contents of the output registers are periodically
copied from the FPGA user application to the FPGA local bus interface.

Consider that the host is trying to read data from the FIFO which is
written by the FPGA logic. There must be a way to signal the FPGA design
for the read operation such that the FIFO will present the new data on
its output port in the next clock cycle. This read signal can be either
generated

1. by a independent write to a certain register location, or 
2. by a synchronized version of the read signal. (By default, there is
no register read signal to the FPGA user application and thus the user
logic has no idea when and what the host program is reading the
registers.) 

In the first way, the round trip delay in the synchronization circuit
may allow the host program to read the old contents from the FIFO output
before the write signal take effect on the FPGA side. This is not
happing in the second way but we still cannot guarantee when data are
ready in a continues way (burst mode) due to the synchronization delay
of the read signal.

In summary, a asynchronous FIFO such like those dual-port BlockRAM will
be best under this situation. But it requires modification of the
"admxrc5t2_main" component and breaks the uniform structure of
synchronizing the register contents.

There is no problem for host to write to a FIFO in the register space
since the write signal and data arrive "user_app" at the same time after
synchronization.