Security and Design Validation
- Anomaly detection, network flow analysis and firewall processors
A. Bara, X. Niu and W. Luk, A Dataflow System for Anomaly Detection and Analysis, International Conference on Field Programmable Technology, 2014.
S. Yusuf, W. Luk, M. Sloman, N. Dulay, E.C. Lupu and G. Brown, Reconfigurable Architecture for Network Flow Analysis, IEEE Transactions on VLSI Systems, vol. 16, no. 1, pp. 57-65, January 2008.
T.K. Lee, S. Yusuf, W. Luk, M. Sloman, E. Lupu and N. Dulay, Compiling Policy Descriptions into Reconfigurable Firewall Processors, Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 39-48, 2003.
S. Yusuf and W. Luk, Bitwise Optimised CAM for Network Intrusion Detection Systems, Proc. International Conference on Field Programmable Logic and Applications, pp. 444-449, 2005.
- Hardware-accelerated cryptographic designs
A. Le Masle and W. Luk, Mapping Loop Structures onto Parametrized Hardware Pipelines, IEEE Transactions on VLSI Systems, vol. 22, no. 3, pp. 631-640, March 2014.
R.C.C. Cheung, N. Telle, W. Luk, and P.Y.K. Cheung, Customisable Elliptic Curve Cryptosystems, IEEE Transactions on VLSI Systems, vol. 13, no. 9, pp. 1048-1059, September 2005.
A. Le Masle, W. Luk, J. Eldredge and K. Carver, Parametric Encryption Hardware Design, Proc. International Symposium on Applied Reconfigurable Computing, LNCS 5992, pp. 68-79, 2010.
A. Le Masle, W. Luk and C.A. Moritz, Parametrized Hardware Architectures for the Lucas Primality Test, Proc. International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, 2011.
G.C.T. Chow, K. Eguro, W. Luk and P.H.W. Leong, A Karatsuba-based Montgomery Multiplier, Proc. International Conference on Field Programmable Logic and Applications, pp. 434-437, 2010.
R.C.C. Cheung, A. Brown, W. Luk and P.K.Y. Cheung, A Scalable Hardware Architecture for Prime Number Validation, Proc. International Conference on Field Programmable Technology, pp. 177-184, 2004.
- Hardware platform for key search engine
O. Mencer, K.H. Tsoi, S. Craimer, T.J. Todman and W. Luk, CUBE: a 512-FPGA Cluster, Proc. Southern Programmable Logic Conference, 2009.
- Detecting and resisting power attack
A. Le Masle, G.C.T. Chow and W. Luk, Constant Power Reconfigurable Computing, Proc. International Conference on Field Programmable Technology, 2011.
A. Le Masle and W. Luk, Detecting Power Attacks on Reconfigurable Hardware, Proc. International Conference on Field Programmable Logic, 2012.
- Security-aware cache
M. Kurek, I. Ilkos and W. Luk, Customizable Security-Aware Cache for FPGA-based Soft Processors, Proc. Southern Programmable Logic Conference, 2011.
- Image registration for watermark restoration
W.J.C. Melis, P.Y.K. Cheung and W. Luk, Image Registration of Real-Time Video Data using the SONIC Reconfigurable Computer Platform, Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, 2002.
- Design validation
N. Ng, N. Yoshida and W. Luk, Scalable Session Programming for Heterogeneous High-Performance Systems, SEFM Workshops, pp. 82-98, 2013.
N. Ng, N. Yoshida, X. Niu, K.H. Tsoi and W. Luk, Session Types: Towards Safe and Fast Reconfigurable Programming, ACM SIGARCH Computer Architecture News, vol. 40, no.5, pp. 22-27, December 2012.
K.W. Susanto and W. Luk, Automating Formal Verification of Customized Soft Processors, Proc. International Conference on Field-Programmable Technology, 2011.
K.W. Susanto, T.J. Todman, J.G.F. Coutinho and W. Luk, Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation, Proc. International Conference on Current Trends in Theory and Practice of Computer Science, 2009.
S.W. McKeever and W. Luk, Provably-Correct Hardware Compilation Tools based on Pass Separation Techniques, Formal Aspects of Computing, vol. 18, no. 2, pp. 120-142, June 2006.
S.W. McKeever, W. Luk and A. Derbyshire, Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries, Proc. International Conference on Formal Methods in Computer-Aided Design, LNCS 2517, pp. 342-359, 2002.
S.R. Guo and W. Luk, An Integrated System for Developing Regular Array Designs, Journal of Systems Architecture, vol. 47, no. 3-4, pp. 315-337, April 2001.
J.W. O'Leary, G.M. Brown and W. Luk, Verified Compilation of Communicating Processes into Clocked Circuits, Formal Aspects of Computing, vol. 9, no. 5-6, pp. 537-559, 1998.
J. He, G. Brown, W. Luk and J. O'Leary, Deriving Two-Phase Modules for a Multi-target Hardware Compiler, in Designing Correct Circuits, Springer Electronic Workshop in Computing series, 1996.
W. Luk, A Declarative Approach to Incremental Custom Computing, Proc. International Synposium on Field-Programmable Custom Computing Machines, 1995.
W. Luk, Systematic Serialisation of Array-based Architectures, Integration, the VLSI Journal, vol. 14, no. 3, pp. 333-360, February 1993.
W. Luk and G. Brown, A systolic LRU Processor and its Top-down Development, Science of Computer Programming, vol. 15, no. 23, pp. 217-233, December 1990.