We have authored many papers on developing designs that target run-time reconfigurable systems. As an example, the following is among the earliest on optimizing hardware designs involving run-time reconfiguration; Xilinx's JBitsDiff tool (FCCM'00, pp. 153-161) follows the ConfigDiff tool described in this paper, which extracts the difference between two successive configurations:

• W. Luk, N. Shirazi and P.Y.K. Cheung, Compilation tools for run-time reconfigurable designs, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 56-65, IEEE Computer Society Press, 1997.

This paper has a journal version.

The following shows ome of our publications in various areas of run-time reconfigurable design.

• Design targeting run-time reconfigurable devices

  X. Niu, T.C.P. Chau, Q. Jin, W. Luk and Q. Liu, Automating elimination of idle functions by run-time reconfiguration, Proc. IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2013.

  M. Koester, W. Luk, J. Hagemeyer, M. Porrmann and U. Ruckert, Design optimizations for tiled partially reconfigurable systems, IEEE Transactions on VLSI Systems, vol. 19, no. 6, pp. 1048-1061, June 2011.

  T. Becker, M. Koester and W. Luk, Automated placement of reconfigurable regions for relocatable modules, in Proc. International Symposium on Circuits and Systems (ISCAS), pp. 3341-3344, 2010.

  T. Becker, W. Luk and Peter Cheung, Enhancing relocatability of partial bitstreams for run-time reconfiguration, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 35-44, IEEE Computer Society Press, 2007.

  M. Weinhardt and W. Luk, Pipeline vectorization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 234-248, February 2001.

  N. Shirazi, W. Luk and P.Y.K. Cheung, Run-time management of dynamically reconfigurable designs, in Field-Programmable Logic and Applications, R.W. Hartenstein and A. Keevallik (editors), LNCS 1482, pp. 59-68, Springer, 1998.

  N. Shirazi, W. Luk and P.Y.K. Cheung, Automating production of run-time reconfigurable designs, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 147-156, IEEE Computer Society Press, 1998.

  W. Luk, N. Shirazi and P.Y.K. Cheung, Modelling and optimising run-time reconfigurable systems, in Proc. IEEE Symposium on FPGAs for Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 167-176, IEEE Computer Society Press, 1996.

• Analytical modelling of performance and energy efficiency

  T. Becker, W. Luk and P.Y.K. Cheung, Energy-aware optimisation for run-time reconfiguration, Proc. IEEE Symp. on Field-Programmable custom Computing Machines (FCCM), IEEE Computer Society, 2010.

  T. Becker, W. Luk and P.Y.K. Cheung, Parametric design for reconfigurable software-defined radio, Proc. Int. Symp. on Applied Reconfigurable Computing (ARC), LNCS 5453, pp. 15-25, 2009.

• Reconfigurable systems and applications

  T. Becker, Q. Jin, W. Luk, and S. Weston, Dynamic constant reconfiguration for explicit finite difference option pricing, Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), pp. 176-181, IEEE Computer Society, 2011.

  P. Sedcole, P.Y.K. Cheung, G.A. Constantinides and W. Luk, Run-time integration of reconfigurable video processing systems, IEEE Transactions on VLSI Systems, vol. 15, no. 9, pp. 1003-1016, September 2007.

  J. Gause, P.Y.K. Cheung and W. Luk, Reconfigurable shape-adaptive template matching architectures, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 2002.

  W. Luk, N. Shirazi, S. Guo and P.Y.K. Cheung, Pipeline morphing and virtual pipelines, in Field-Programmable Logic and Applications, W. Luk, P.Y.K. Cheung and M. Glesner (editors), LNCS 1304, pp. 111-120, Springer 1997.

  N. Shirazi, D. Benyamin, W. Luk, P.Y.K. Cheung and S. Guo, Quantitative analysis of FPGA-based database searching, Journal of VLSI Signal Processing, vol 28, no. 1-2, May 2001.

• Dynamic clocking and voltage scaling

  J.A. Bower, W. Luk, O. Mencer, M.J. Flynn and M. Morf, Dynamic clock-frequencies for FPGAs, Microprocessors and Microsystems, vol. 30, no. 6, pp. 388-397, September 2006.

  C.T. Chow, L.S.M. Tsui, P.H.W. Leong, W. Luk and S.J.E. Wilton, Dynamic voltage scaling for commercial FPGAs, Proc. IEEE Int. Conf. on Field-Programmable Technology, 2005.

• Program branch probabilities and phase optimisation

  H. Styles and W. Luk, Compilation and management of phase-optimised reconfigurable systems, Proc. FPL, 2005.

  H. Styles and W. Luk, Exploiting program branch probabilities in hardware compilation, IEEE Transactions on Computers, vol. 53, no. 11, pp. 1408-1419, November 2004.

• Run-time adaptive instruction processor design

  S. Seng, W. Luk and P.Y.K. Cheung, Run-Time Adaptive Flexible Instruction Processors, Processings of International Conference on Field-Programmable Logic, LNCS 2438, 2002, pp. 545-555.