- Machine Learning for Quantum Computing
H. Fan, C. Guo and W. Luk, Optimizing Quantum Circuit Placement via Machine Learning, Design Automation Conference, 2022.
- Accelerating Convolutional Neural Networks and Perceptrons
H. Fan, S. Liu, Z. Que, X. Niu and W. Luk, High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point, Accepted for publication, IEEE Transactions on Neural Networks and Learning Systems, 2022.
S. Liu, H. Fan, M. Ferianc, X. Niu, H. Shi and W. Luk, Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs, Accepted for publication, IEEE Transactions on Neural Networks and Learning Systems, 2021. S. Liu, H. Fan and W,Luk, Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA, Design Automation and Test Europe, 2021. H. Fan, M. Ferianc, S. Liu, Z. Que, X. Niu and W. Luk, Optimizing FPGA-Based CNN Accelerator using Differentiable Neural Architecture Search, IEEE International Conference on Computer Design, 2020. H. Nakahara, Z. Que and W. Luk, High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression, IEEE International Symposium on Field-Programmable Custom Computing Machines, 2020. (Best Paper Award candidate) R. Zhao, W. Luk, C. Xiong, X. Niu and K.H. Tsoi, On the Challenges in Programming Mixed-Precision Deep Neural Networks, 4th ACM SIGPLAN International Workshop on Machine Learning and Programming Languages, 2020. H. Fan, C. Luo, C. Zeng, M. Ferianc, Z. Que, S. Liu, X. Niu and W. Luk, F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2019. (Best Paper Award candidate) S. Liu, R.S.W. Chu, X. Wang and W. Luk, Optimizing CNN-based hyperspectral image classification on FPGAs, International Symposium on Applied Reconfigurable Computing, 2019. S. Liu and W. Luk, Towards an efficient accelerator for DNN-based remote sensing image segmentation on FPGAs, International Conference on Field Programmable Logic and Applications, 2019. H. Fan, S. Liu, M. Ferianc, H.C. Ng, Z. Que, S. Liu, X. Niu and W. Luk, A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA , International Conference on Field-Programmable Technology, 2018. (Best Paper Award candidate) S. Liu, H. Fan, X. Niu, H.C. Ng, Y. Chu and W. Luk, Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA, ACM Transactions on Reconfigurable Technology and Systems, vol. 11, issue 3, article no. 19, December 2018. R. Zhao, H.C. Ng, W. Luk and X. Niu, Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA, International Conference on Field-Programmable Logic and Applications, 2018. H. Fan, H.C. Ng, S. Liu, Z. Que, X. Niu and W. Luk, Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation, International Conference on Field-Programmable Logic and Applications, 2018. X. Fan, D. Wu, W. Cao, W. Luk and L. Wang, Stream Processing Dual-Track CGRA for Object Inference, IEEE Transactions on VLSI Systems, vol. 26, no. 6, pp. 1098-1111, 2018. S. Liang, S. Yin, L. Liu, W. Luk and S. Wei, FP-BNN: Binarized Neural Network on FPGA, Neurocomputing, vol. 275, pp. 1072-1086, January 2018. R. Zhao, S. Liu, H.C. Ng, E. Wang, J.J. Davies, X. Niu, X. Wang, H. Shi, G.A. Constantinides, P.Y.K. Cheung and W. Luk, Hardware Compilation of Deep Neural Networks: An Overview, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2018. J. Gao, Y. Zhu, M. Qiu, K.H. Tsoi, X. Niu, W. Luk, R. Zhao, Z. Que, W. Mao, C. Feng, X. Zha, G. Deng, J. Chen and T.Liu, Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform, SmartCom 2018. N. Voss, M. Bacis, O. Mencer, G. Gaydadjiev and W. Luk, Convolutional Neural Networks on Dataflow Engines, IEEE International Conference on Computer Design, 2017. H. Fan, X. Niu, Q. Liu and W. Luk, F-C3D: FPGA-based 3-Dimensional Convolutional Neural Network, International Conference on Field Programmable Logic and Applications, 2017. R. Zhao, W. Luk, X. Niu, H. Shi and H. Wang, Hardware Acceleration for Machine Learning, IEEE Computer Society Annual Symposium on VLSI, 2017. R. Zhao, X. Niu, Y. Wu, W. Luk and Q. Liu, Optimizing CNN-based Object Detection Algorithms on Embedded FPGA Platforms, International Symposium on Applied Reconfigurable Computing, 2017. W. Luk, A. Lawrence, V. Lok, I. Page and R. Stamper, Parametrised Neural Network Design and Compilation into Hardware, in VLSI for Neural Networks and Artificial Intelligence, J.G. Delgado-Frias (editor), Plenum Press, 1994. - Accelerating Neural Network Training
R. Zhao, B. Vogel, T. Ahmed and W. Luk,
Reducing Underflow in Mixed Precision Training by Gradient Scaling,
International Joint Conference on Artificial Intelligence, 2020.
C. Luo, M. Sit, H. Fan, S. Liu, W. Luk and C. Guo,
Towards Efficient Deep Neural Network Training by FPGA-based Batch-level Parallelism,
Journal of Semiconductors, vol. 41, no. 2, Article 022403, 2020.
W. Zhao, H. Fu, W. Luk, T. Yu, S. Wang, B. Feng, Y. Ma and G. Yang,
F-CNN: An FPGA-based Framework for Training Convolutional Neural Networks,
IEEE International Conference on Application-specific Systems,
Architectures and Processors, 2016.
- Neural Architecture Search
H. Fan, M. Ferianc, Z. Que, H. Li, S. Liu, X. Niu and W. Luk,
Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator,
27th Asia and South Pacific Design Automation Conference, 2022.
H. Fan, M. Ferianc, S. Liu, Z. Que, X. Niu and W. Luk,
Optimizing FPGA-Based CNN Accelerator using Differentiable Neural Architecture Search,
IEEE International Conference on Computer Design, 2020.
- Neural Architecture Debug and Tuning
Z. Que, D.H. Noronha, R. Zhao, X. Niu, S.J.E. Wilton and W. Luk,
In-circuit Tuning of Deep Learning Designs,
Journal of Systems Architecture,
Vol. 118, September 2021.
D.H. Noronha, Z. Que, W. Luk and S.J.E. Wilton,
Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs,
IEEE International Symposium on
Field-Programmable Custom Computing Machines, 2021.
D.H. Noronha, R. Zhao, Z. Que, J. Goeders, W. Luk and S.J.E. Wilton,
An Overlay for Rapid FPGA Debug of Machine Learning Applications,
International Conference on Field-Programmable Technology, 2019.
(Best Paper Award candidate)
D.H. Noronha, R. Zhao, J. Goeders, W. Luk and S.J.E. Wilton,
On-chip FPGA Debug Instrumentation for Machine Learning Applications,
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
- Spiking Neural Networks: Acceleration and Applications
K. Gao, W. Luk and S. Weston,
High-frequency trading and financial time-series prediction with spiking neural networks,
Wilmott, Vol. 2021, no. 113, pp. 18-23, May 2021.
M. Shahsavari, D.B. Thomas, A. Brown and W. Luk,
Neuromorphic Design using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture,
International Conference on Neuromorphic Systems, 2021.
K. Cheung, S.R. Schultz and W. Luk,
NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors,
Frontiers in Neuroscience, 14 January 2016.
D.B. Thomas and W. Luk,
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks,
IEEE International Symposium on
Field-Programmable Custom Computing Machines, 2009.
- Accelerating Recurrent Neural Networks
Z. Que, H. Nakahara, E. Nurvitadhi, A. Boutros, H. Fan, C. Zeng, J. Meng, K.H. Tsoi, X. Niu and W. Luk, Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs, IEEE Transactions on VLSI Systems, vol. 30, no. 2, pp. 227-237, 2022.
Z. Que, E. Wang, U. Marikar, E.A. Moreno, J. Ngadiuba, H. Javed, B. Borzyszkowski, T. Aarrestad, V. Loncar, S. Summers, M. Pierini, P.Y.K. Cheung and W. Luk, Accelerating Recurrent Neural Networks for Gravitational Wave Experiments, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2021.
Z. Que, H. Nakahara, E. Nurvitadhi, H. Fan, C. Zeng, J. Meng, X. Niu and W. Luk, Optimizing Reconfigurable Recurrent Neural Networks, IEEE International Symposium on Field-Programmable Custom Computing Machines, 2020. Z. Que, T. Nugent, S. Liu, L. Tian, X. Niu, Y. Zhu and W. Luk, Efficient Weight Reuse for Large LSTMs, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2019. Z. Que, Y. Liu, C. Guo, X. Niu, Y. Zhu and W. Luk, Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM, International Conference on Field Programmable Technology, 2019. H. Zhu, Y. Zhu, D. Wu, H. Wang, L. Tian, W. Mao, C. Feng, X. Zha, G. Deng, J. Chen, T. Liu, X. Niu, K.H. Tsoi and W. Luk, Correlation Coefficient Based Cluster Data Preprocessing and LSTM Prediction Model for Time Series Data in Large Aircraft Test Flights, SmartCom 2018. - Accelerating Bayesian Neural Networks
H. Fan, M. Ferianc, Z. Que, X. Niu, M. Rodrigues, and W. Luk, Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations, IEEE Transactions on Parallel and Distributed Systems, early acccess, 2022.
H. Fan, M. Ferianc, Z. Que, S. Liu, X. Niu, M. Rodrigues, and W. Luk, FPGA-based Acceleration for Bayesian Convolutional Neural Networks, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, early acccess, 2022.
H. Fan, M. Ferianc and W. Luk, Enabling Fast Uncertainty Estimation: Accelerating Bayesian Transformers via Algorithmic and Hardware Optimizations, Design Automation Conference, 2022.
M. Ferianc, Z. Que, H. Fan, W. Luk and M. Rodrigues, Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator, International Conference on Field Programmable Technology, 2021.
H. Fan, M. Ferianc, M. Rodrigues, H. Zhou, X. Niu and W. Luk, High-Performance FPGA-based Accelerator for Bayesian Neural Networks, Design Automation Conference, 2021.
- Accelerating Graph Neural Networks
Z. Que, M. Loo, H. Fan, M. Pierini, A. Tapper and W. Luk, Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs, International Conference on Field Programmable Logic and Applications, 2022.
Z. Que, M. Loo and W. Luk, Reconfigurable Acceleration of Graph Neural Networks for Jet Identification in Particle Physics, International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022.
- Accelerating Generative Networks
S. Liu, C. Zeng, H. Fan, H.C. Ng, J. Meng, Z. Que, X. Niu and W. Luk, Memory-Efficient Architecture for Accelerating Generative Networks on FPGA, International Conference on Field Porgrammable Technology, 2018.
- Accelerating Causal Discovery
C. Guo and W. Luk, Accelerating Constraint-Based Causal Discovery by Shifting Speed Bottleneck, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2022.
- Accelerating Gaussian Mixture Models
C. He, H. Fu, C. Guo, W. Luk and G. Yang, A Fully-Pipelined Hardware Design for Gaussian Mixture Models, IEEE Transactions on Computers, vol. 66, no. 11, pp. 1837-1850, November 2017.
C. Guo, H. Fu and W. Luk, A Fully-Pipelined Expectation-Maximization Engine for Gaussian Mixture Models, International Conference on Field-Programmable Technology, 2012.
- Accelerating Support Vector Machine for Finance, Hyperspectral Image Classification, and Anomaly Detection
S. Shao, O. Mencer and W. Luk, Dataflow Design for Optimal Incremental SVM Training, International Conference on Field-Programmable Technology, 2016.
S. Wang, X. Niu, N. Ma, W. Luk, P. Leong and Y. Peng, A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification, International Symposium on Applied Reconfigurable Computing, 2016.
A. Bara, X. Niu and W. Luk, A Dataflow System for Anomaly Detection and Analysis, International Conference on Field-Programmable Technology, 2014.
- Accelerating Reinforcement Learning
C. Guo, W. Luk, S.L.Q. Shui, A. Warren and J. Levine, Customisable Control Policy Learning for Robotics, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2019.
S. Shao J. Tsai, M. Mysior, W. Luk, T. Chau, A. Warren and B. Jeppesen, Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2018.
S. Shao and W. Luk, Customised Pearlmutter Propagation: A Hardware Architecture for Trust Region Policy Optimisation, International Conference on Field-Programmable Technology, 2017.
- Accelerating Inductive Logic Programming
A.K. Fidjeland, W. Luk and S.H. Muggleton, Customisable Multi-Processor Acceleration of Inductive Logic Programming, in Latest Advances in Inductive Logic Programming, S.H. Muggleton and H. Watanabe (editors), Imperial College Press, 2015.
A. Fidjeland, W. Luk and S.H. Muggleton, A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming, Proc. Visions of Computer Science - BCS International Academic Conference, September 2008.
A. Fidjeland, W. Luk and S.H. Muggleton, Scalable Acceleration of Inductive Logic Programs, International Conference on Field-Programmable Technology, 2002.
- Accelerating Genetic Algorithms and Regression and Regularisation Solvers
A. Cross, L. Guo, W. Luk and M. Salmon, CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems, International Conference on Field-Programmable Logic and Applications, 2018.
L. Guo, A.I. Funie, D.B. Thomas, H. Fu and W. Luk, Parallel Genetic Algorithms on Multiple FPGAs, ACM SIGARCH Computer Architecture News, Vol. 43, No. 4, September 2015.
L. Guo, A.I. Funie, Z. Zie, D.B. Thomas and W. Luk, A General-Purpose Framework for FPGA-accelerated Genetic Algorithms, International Journal of Bio-Inspired Computation (IJBIC), Vol. 7, No. 6, 2015.
S. Shao, L. Guo, C. Guo, T.C.P. Chau, D.B. Thomas and W. Luk, Recursive Pipelined Genetic Propagation for Bilevel Optimisationg, International Conference on Field-Programmable Technology, 2015.
L. Guo, C. Guo, D.B. Thomas and W. Luk, Pipelined Genetic Propagation, IEEE International Symposium on Field-Programmable Custom Computing Machines, 2015.
A.I. Funie, P. Grigoras, P. Burovskiy, W. Luk and M. Salmon, Reconfigurable Acceleration of Fitness Evaluation in Trading Strategies, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2015.
L. Guo, D.B. Thomas and W. Luk, An Automated Framework for General-Purpose Genetic Algorithms in FPGAs, European Conference on the Applications of Evolutionary Computation, 2014.
A.I. Funie, M. Salmon and W. Luk, A Hybrid Genetic-Programming Swarm-Optimisation Approach for Examining the Nature and Stability of High Frequency Trading Strategies, International Conference on Machine Learning and Applications, 2014.
- Machine Learning for Accelerator Design
M. Ferianc, H. Fan, D. Manocha, H. Zhou, S. Liu, X. Niu and W. Luk, Improving performance estimation for design space exploration for convolutional neural network accelerators, Electronics, 10(4):520, February 2021.
M. Kurek, M.P. Deisnroth, W. Luk and T. Todman, Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs, IEEE International Symposium on Field-Programmable Custom Computing Machines, 2016.
T.C.P. Chau, M. Kurek, J.S. Targett, J. Humphrey, G. Skouroupathis, A. Eele, J. Maciejowski, B. Cope, K. Cobden, P. Leong, P.Y.K. Cheung and W. Luk, SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications, IEEE International Symposium on Field-Programmable Custom Computing Machines, 2014.
M. Kurek, T. Becker, T.C.P. Chau and W. Luk, Automating Optimization of Reconfigurable Designs, IEEE International Symposium on Field-Programmable Custom Computing Machines, 2014.
M. Kurek and W. Luk, Parametric Reconfigurable Designs with Machine Learning Optimizer, Proc. International Conference on Field-Programmable Technology, 2012.