Much of the fundamental research was supported by the EPSRC grants Optimising Hardware Acceleration for Financial Computation and SONNETS: Scalability Oriented Novel Network of Event Triggered Systems.

• K. Gao, S. Weston, P. Vytelingum, N.R. Stillman, W. Luk and C. Guo, Deeper Hedging: a new agent-based model for effective deep hedging, 4th ACM International Conference on AI in Finance (ICAIF), 2023.

• K. Gao, P. Vytelingum, S. Weston, W. Luk and C. Guo, High-frequency financial market simulation and flash crash scenarios analysis: an agent-based modelling approach, arXiv:2208.13654, August 2022.

• K. Gao, P. Vytelingum, S. Weston, W. Luk and C. Guo, Understanding intra-day price formation process by agent-based financial market simulation: calibrating the Extended Chiarella Model, Wilmott, Vol. 2022, no. 119, pp. 22-38, May 2022.

• K. Gao, W. Luk and S. Weston, High-frequency trading and financial time-series prediction with spiking neural networks, Wilmott, Vol. 2021, no. 113, pp. 18-23, May 2021.

• P. Papaphilippou, C. Brooks and W. Luk, An adaptable high-throughput FPGA merge sorter for accelerating database analytics, Proc. Int. Conf. on Field Programmable Logic and Applications, 2020.

• A.-I. Funie, P. Grigoras, P. Burovskiy, W. Luk and M. Salmon, Run-time reconfigurable acceleration for genetic programming fitness evaluation in trading strategies, Journal of Signal Processing Systems, 90(1):39-52, 2018.

• A.-I. Cross, L. Guo, W. Luk and M. Salmon, CRRS: Custom Regression and Regularisation Solver for large-scale linear systems, Proc. Int. Conf. on Field Programmable Logic and Applications, 2018.

• A.-I. Cross, L. Guo, W. Luk and M. Salmon, CJS: Custom Jacobi Solver, Proc. Int. Symp. on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), 2018.

• G. Inggs, D. Thomas and W. Luk, A domain specific approach to high performance heterogeneous computing, IEEE Transactions on Parallel and Distributed Systems, vol. 28, no. 1, pp. 2-15, 2017.

• C. He, H. Fu, W. Luk, W. Li and G. Yang, Exploring the potential of reconfigurable platforms for order book update, Proc. Int. Conf. on Field Programmable Logic and Applications, 2017.

• H. Fu, C. He, W. Luk, W. Li and G. Yang, A nanosecond-level hybrid table design for financial market data generators, Proc. Int. Conf. on Field Programmable Custom Computing Machines, 2017.

• S. Shao, O. Mencer and W. Luk, Dataflow Design for Optimal Incremental SVM Training, International Conference on Field-Programmable Technology, 2016.

• B. Lindsey, M. Leslie and W. Luk, A domain specific language for accelerated multilevel Monte Carlo simulations, Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, 2016. (Best Paper Award)

• A.I. Funie, P. Grigoras, P. Burovskiy, W. Luk and M. Salmon, Reconfigurable Acceleration of Fitness Evaluation in Trading Strategies, Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, 2015.

• S. Shao, C. Guo, W. Luk and S. Weston, Accelerating transfer entropy computation, Proc. Int. Conf. on Field Programmable Technology, 2014.

• J. Yang, C. Guo, W. Luk and T. Nahar, Collaborative processing of Least-Square Monte Carlo for American Options, Proc. Int. Conf. on Field Programmable Technology, 2014.

• X. Niu, Q. Jin, W. Luk and S. Weston, A self-aware tuning and self-aware evaluation method for finite-difference applications in reconfigurable systems, ACM Transactions on Reconfigurable Technology and Systems, vol. 7, no. 2, Article 15, June 2014.

• C. Guo and W. Luk, Pipelined HAC estimation engines for multivariate time series, Journal of Signal Processing Systems, vol. 77, pp. 117-129, 2014.

• S. Denholm, H. Inoue, T. Takenaka, T. Becker and W. Luk, Low latency FPGA acceleration of market data feed arbitration, Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, 2014.

• C. Guo, W. Luk and S. Weston, Pipelined reconfigurable accelerator for ordinal pattern encoding, Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, 2014.

• C. Guo and W. Luk, Accelerating parameter estimation for multivariate self-exciting point processes, Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014.

• C. Guo and W. Luk, Accelerating HAC estimation for multivariate time series, Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, 2013. (Best Paper Award)

• C. Guo, W. Luk, E. Vinkovskaya and R. Cont, Customisable pipelined engine for intensity evaluation in multivariate Hawkes point processes, ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 59-64, December 2013.

• X. Niu, T.C.P. Chau, Q. Jin, W. Luk and Q. Liu, Automating elimination of idle functions by run-time reconfiguration, Proc. IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2013.

• H. Ruan, X. Huang, H. Fu, G. Yang, W. Luk, S. Racaniere, O. Pell and W. Han, An FPGA-based Data Flow Engine For Gaussian copula model, Proc. IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2013.

• A.H.T. Tse, D. Thomas and W. Luk, Design exploration of quadrature methods in option pricing, IEEE Transactions on VLSI Systems, vol. 20, no. 5, pp. 818-826, May 2012.

• G.C.T. Chow, A.H.T. Tse, Q. Jin, W. Luk, P.H.W. Leong and D.B. Thomas, A mixed precision Monte Carlo methodology for reconfigurable accelerator systems, Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 57-66, 2012.

• Q. Jin, D. Dong, A.H.T. Tse, G.C.T. Chow, D.B. Thomas, W. Luk and S. Weston, Multi-level customisation framework for curve based Monte Carlo financial simulations, Proc. International Conference on Applied Reconfigurable Computing, pp. 187-201, 2012. (Best Paper Award)

• A.H.T. Tse, G.C.T. Chow, Q. Jin, D.B. Thomas and W. Luk, Optimising performance of quadrature methods with reduced precision, Proc. International Conference on Applied Reconfigurable Computing, pp. 251-263, 2012.

• T. Becker, Q. Jin, Wayne Luk and S. Weston, Dynamic constant reconfiguration for explicit finite difference option pricing, Proc. International Conference on ReConFigurable Computing and FPGAs, 2011.

• C.Y. Yu, A.M. Smith, W. Luk, P.H.W. Leong and S.J.E. Wilton, Optimizing floating point units in hybrid FPGAs, IEEE Transactions on VLSI Systems, vol. 20, no. 7, pp. 1295-1303, July 2012. (The bgm benchmark involves Monte Carlo simulations based on the Brace, Gatarek, and Musiela (BGM) model.)

• Q. Jin, D.B. Thomas and W. Luk, On comparing financial option price solvers on FPGA, Proc. IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2011.

• S. Wray and W. Luk, Exploring algorithmic trading in reconfigurable hardware, Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, 2010.

• A.H.T. Tse, D. Thomas, K.H. Tsoi and W. Luk, Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters, Proc. Int. Conf. on Field-Programmable Technology, 2010.

• A.H.T. Tse, D. Thomas, K.H. Tsoi and W. Luk, Efficient reconfigurable design for pricing Asian options, SIGARCH Computer Architecture News, 38(4):14-20, 2010.

• S. Wray, W. Luk and P. Pietzuch, Run-time reconfiguration for a reconfigurable algorithmic trading engine, Proc. Int. Conf. on Field-Programmable Logic and Applications, 2010.

• C.H. Ho, C.W. Yu, P.H.W. Leong, W. Luk and S.J.E. Wilton, Floating-point FPGA: architecture and modeling, IEEE Transactions on VLSI Systems, vol. 17, no. 12, pp. 1709-1718, December 2009. (The bgm benchmark involves Monte Carlo simulations based on the BGM model. The conference version of this paper won the Stamatis Vassiliadis Award at FPL 2007.)

• G.W. Morris, D.B. Thomas and W. Luk, FPGA accelerated low-latency market data feed processing, Proc. High Performance Interconnects, pp. 83-89, 2009.

• Q. Jin, D.B. Thomas, W. Luk and B. Cope, Exploring reconfigurable architectures for tree-based option pricing models, ACM Transactions on Reconfigurable Technology and Systems, Volume 2, Issue 4, Article 21, September 2009.

• Q. Jin, D.B. Thomas and W. Luk, Exploring reconfigurable architectures for explicit finite difference option pricing models, Proc. Int. Conf. on Field-Programmable Logic and Applications, 2009.

• D.B. Thomas and W. Luk, Credit risk modelling using hardware accelerated Monte-Carlo simulation, Proc. IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2008.

• C.W. Yu, A.M. Smith, W. Luk, P.H.W. Leong and S.J.E. Wilton, Optimizing coarse-grained units in floating-point hybrid FPGA , Proc. Int. Conf. on Field-Programmable Technology, 2005. (The bgm benchmark involves Monte Carlo simulations based on the BGM model.)

• D.B. Thomas and W. Luk, A domain specific language for reconfigurable path-based Monte Carlo simulations, Proc. Int. Conf. on Field-Programmable Technology, 2007.

• D.B. Thomas, J.A. Bower and W. Luk, Automatic generation and optimization of reconfigurable financial Monte-Carlo simulations, Proc. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors, 2007.

• J.A. Bower, D.B. Thomas, W. Luk and O. Mencer, A reconfigurable simulation framework for financial computation, Proc. Int. Conf. on Reconfigurable Computing and FPGAs, 2006.

• G.L. Zhang, P.H.W. Leong, C.H. Ho, K.H. Tsoi, C.C.C. Cheung, D.U. Lee, R.C.C. Cheung and W. Luk, Reconfigurable acceleration for Monte Carlo based financial simulation, Proc. Int. Conf. on Field-Programmable Technology, 2005. (This is the first paper applying reconfigurable computing to speeding up computational finance.)

The following are papers on random number generators which could be of interest in finance for applications involving, for instance, Monte Carlo simulation.

• D.B. Thomas and W. Luk, Multiplierless algorithm for multivariate gaussian random number generation in FPGAs, IEEE Transactions on VLSI Systems, vol. 21, no. 12, pp. 2193-2205, December 2013..

• D.B. Thomas and W. Luk, The LUT-SR family of uniform random number generators for FPGA architectures, IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp. 761-770, April 2013.

• D.B. Thomas and W. Luk, Multivariate Gaussian random number generation targeting reconfigurable hardware, ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 2, June 2008.

• D.B. Thomas, W. Luk, P.H.W. Leong and J.D. Villasenor, Gaussian random number generators, ACM Computing Surveys, vol. 39, no. 4, pp. 11.1-11.38, October 2007.

• R.C.C. Cheung, D. Lee, W. Luk and J.D. Villasenor, Hardware generation of arbitrary random number distributions from uniform distributions via the inversion method, IEEE Transactions on VLSI Systems, vol. 15, no. 8, pp. 952-962, August 2007.

• D.B. Thomas and W. Luk, Non-uniform random number generation through piecewise linear approximations, IET Proceedings - Computers and Digital Techniques, vol. 1, no. 4, pp. 312-321, July 2007.

• D.B. Thomas and W. Luk, High quality uniform random number generation using LUT optimised state-transition matrices, Journal of VLSI Signal Processing, vol. 47, no. 1, pp. 77-82, April 2007.

• D. Lee, J.D. Villasenor, W. Luk and P.H.W. Leong, A hardware Gaussian noise generator using the Box-Muller method and its error analysis, IEEE Transactions on Computers, vol. 55, no. 6, pp. 659-671, June 2006.

• D. Lee, W. Luk, J.D. Villasenor, G. Zhang and P.H.W. Leong, A hardware Gaussian noise generator using the Wallace method, IEEE Transactions on VLSI Systems, vol. 13, no. 8, pp. 911-920, August 2005.

• D. Lee, W. Luk, J.D. Villasenor and P.Y.K. Cheung, A Gaussian noise generator for hardware-based simulations, IEEE Transactions on Computers, vol. 53, no. 12, pp. 1523-1534, December 2004.