The EURECA architecture
EURECA, which stands for Effective Utilities for Run-timE Configuration Adaptation, is a novel memory architecture for supporting dynamic data access in reconfigurable devices.
Key EURECA features include:
- static and dynamic configuration memory controlled by a multiplexor array and configuration distribution network,
- on-chip configuration generation,
- cycle-by-cycle reconfiguration.
Detailed description of EURECA can be found in:
- X. Niu, W. Luk and Y. Wang, EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access, in Proc. ACM/SIGDA Symposium on Field-Programmable Gate Arrays, 2015. (presentation).
- H. Zhou, X. Niu, J. Yuan, L. Wang and W. Luk, Connect On the Fly: Enhancing and Prototyping of Cycle-Reconfigurable Modules, in Proc. Field Programmable Logic and Applications, 2016.
- X. Niu, N. Ng, T. Yuki, S. Wang, N. Yoshida and W. Luk, EURECA Compilation: Automatic Optimisation of Cycle-Reconfigurable Circuits, in Proc. Field Programmable Logic and Applications, 2016.