We have developed various compilation and optimisation technologies for reconfigurable computing systems. The following provides some examples of our work.

• I. Page and W. Luk, Compiling occam into field-programmable gate arrays, in FPGAs, W. Moore and W. Luk (editors), pp. 271-283, Abingdon EE&CS Books, 1991.

  This paper describes a syntax-directed hardware compilation method for a parallel language. It led to commercial tools including Celoxica's Handel-C compiler and Sharp's Bach-C compiler (ISCAS'99, pp. 366-369). Handel-C has been used extensively in academia and industry; according to Celoxica on admission to London's Alternative Investment Market, there were about 400 commercial seats in October 2005.

• M. Weinhardt and W. Luk, Pipeline vectorization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 234-248, February 2001.

  The first paper on vectorisation and the associated transformations for reconfigurable pipeline architectures. The conference version was published in FCCM'99, pp. 52-62. The proposed techniques were adopted for XPP devices from PACT (Journal of Supercomputing, 26(2):167-184, 2003).

• J.A. Bower, W.N. Cho and W. Luk, Unifying FPGA hardware development, International Conference on Field-Programmable Technology (FPT), pp. 113-120, 2007.

  This paper introduces a unified approach, based on a new domain-specific embedded language, for developing and optimizing both high-level and low-level designs including intellectual properties. It influenced the tools at Maxeler Technologies.

• W. Luk, J.G.F. Coutinho, T. Todman, Y.M. Lam, W. Osborne, K.W. Susanto, Q. Liu and W.S. Wong, A high-level compilation tool chain for heterogeneous systems, IEEE International System-on-Chip (SOC) Conference, pp. 9-18, 2009.

  This paper presents a tool-chain that adopts source-level transformation and mapping selection for multi-processor designs involving embedded processors and FPGAs. The work was commercialized by BlueBee Technologies, including various tools from the hArtes tool chain. BlueBee was acquired by Illumina in June 2020.

• Q. Liu, T. Todman, W. Luk and G.A. Constantinides, Optimizing hardware design by composing utility-directed transformations, IEEE Transactions on Computers, vol. 61, no. 12, pp. 1800-1812, December 2012.

  The first paper to address composition of utility-directed transformations based on techniques such as linear programming or geometric programming. These techniques have shown promise in optimising a wide variety of reconfigurable computing systems, from power adaptive computing for energy harvesting to heterogeneous computing engines.

The following includes links to our papers on compilation and optimisation for reconfigurable computing.

• J. Vandebon, J.G.F. Coutinho, E. Nurvitadhi, T. Todman and W. Luk, Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies,IEEE Symposium on Field-Programmable Custom Computing Machines, 2020.

• P. Grigoras, X. Niu, J.G.F. Coutinho, W. Luk, J.A. Bower and O. Pell, Aspect Driven Compilation for Dataflow Designs, Proc. IEEE International Conference on Application-specific Systems, Architectures and Processors, 2013.

• T. Todman, Q. Liu, W. Luk and G.A. Constantinides, Customizable composition and parameterization of hardware design transformations, Proc. 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, pp. 595-602, 2010.

• K. Bertels, V.-M. Sima, Y. Yankova, G. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto and A. Michelotti, HArtes: Hardware-software codesign for heterogeneous multicore platforms, IEEE Micro, vol. 30, no. 5, pp. 88-97, Sept.-Oct. 2010.

• Y.M. Lam, J.G.F. Coutinho, C.H. Ho, P.H.W. Leong and W. Luk, Multiloop parallelisation using unrolling and fission, International Journal of Reconfigurable Computing, vol. 2010, Article ID 475620, 2010.

• T. Wiangtong, P.Y.K. Cheung and W. Luk, Hardware/software codesign: a systematic approach targeting data-intensive applications, IEEE Signal Processing, vol. 22, no. 3, pp. 14-22, May 2005.

• T. Todman, J.G. de F. Coutinho and W. Luk, Customisable hardware compilation, The Journal of Supercomputing, vol. 32, no. 2, pp. 119-137, May 2005.

• H. Styles and W. Luk, Compilation and management of phase-optimised reconfigurable systems, Proc. FPL, 2005.

• H. Styles and W. Luk, Exploiting program branch probabilities in hardware compilation, IEEE Transactions on Computers, vol. 53, no. 11, pp. 1408-1419, November 2004.

• T. Wiangtong, Peter Y.K. Cheung, W. Luk, Comparing three heuristic search methods for functional partitioning in hardware-software codesign, Journal on Design Automation for Embedded Systems, vol. 6, no. 4, pp. 425-449, July 2002.

• M. Weinhardt and W. Luk, Memory access optimisation for reconfigurable systems, Proc. IEE - Computers and Digital Techniques, vol. 148, no. 3, pp. 105-112, May 2001.

• S.R. Guo and W. Luk, An integrated system for developing regular array designs, Journal of Systems Architecture, vol. 47, no. 3-4, pp. 315-337, April 2001.