Projects

Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies

This project provides a novel compilation approach that addresses the complexity of mapping high-level descriptions to heterogeneous platforms, improving design productivity and maintainability. The approach is based on a co-design methodology decoupling functional concerns from optimisation concerns, allowing two separate descriptions to be independently maintained by two types of programmers: application experts focus on algorithmic behaviour, while platform experts focus on the mapping process. Our approach supports two key requirements: (1) Customisable optimisations to rapidly capture a wide range of mapping strategies, and (2) Reusable strategies to allow optimisations to be described once and applied to multiple applications. To evaluate our approach, we develop Artisan, a meta-programming tool for codifying optimisation strategies using a high-level general-purpose programming language (Python 3), offering full design-flow orchestration of key components (sourcecode, third-party tools, and platforms). We evaluate Artisan using three case study applications and three reusable optimisation strategies, achieving at least 24 times speedup for each application on CPU and FPGA targets with little application developer effort.

Specifying Compiler Strategies for FPGA-based Systems

The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is typically a long and error-prone process. In addition to developing the required functions, developers need to be deeply involved on code transformations and optimizations to achieve the required performance. This project explores the use of a novel aspect-oriented hardware/software design-flow for FPGA-based embedded platforms. The design-flow uses LARA, a domain-specific aspect-oriented programming language devoted to high-level specifications of compilation and application mapping strategies, which are sequences of data/computation transformations and optimizations. With LARA, developers are able to guide a design-flow to partition an application between hardware and software components and orchestrate its execution on alternative architectures. We illustrate the use of LARA on two complex real-life applications using high-level compilation and synthesis strategies for achieving complete hardware/software implementations with speedups of 2.5 to 6.8 times over software-only implementations. As the approach described allows developers to maintain a single application source code, it promotes developer productivity as well as code and performance portability.

LARA: An Aspect-Oriented Programming Language for Embedded Systems

The development of applications for high-performance embedded systems is typically a long and error-prone process. In addition to the required functions, developers must consider various and often conflicting non-functional application requirements such as performance and energy efficiency. The complexity of this process is exacerbated by the multitude of target architectures and the associated retargetable mapping tools. This project introduces an Aspect- Oriented Programming (AOP) approach that conveys domain knowledge and non-functional requirements to optimizers and mapping tools. We describe a novel AOP language, LARA, which allows the specification of compilation strategies to enable efficient generation of software code and hardware cores for alternative target architectures. We illustrate the use of LARA for code instrumentation and analysis, and for guiding the application of compiler and hardware synthesis optimizations. An important LARA feature is its capability to deal with different join points, action models, and attributes, and to generate an aspect intermediate representation. We present examples of our aspect-oriented hardware/software design flow for mapping real-life application codes to embedded platforms based on Field Programmable Gate Array (FPGA) technology.

A New Approach to Control and Guide the Mapping of Computations to FPGAs

Field-Programmable Gate-Arrays (FPGAs) are becoming increasingly popular as computing platforms for high-performance embedded systems. Their flexibility and customization capabilities allow them to achieve orders of magnitude better performance than conventional embedded computing systems. Programming FPGAs is, however, cumbersome and error-prone and as a result their true potential is often only achieved at unreasonably high design efforts. The REFLECT (Rendering FPGAs to Multi-Core Embedded Computing) project.s design flow consists of a novel compilation and synthesis system approach for FPGAbased platforms. Its design flow relies on Aspect-Oriented Specifications to convey critical domain knowledge to optimizers and mapping engines. An aspect-oriented programming language, LARA (LAnguage for Reconfigurable Architectures), allows the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be incorporated into larger multi-core designs. We are evaluating the effectiveness of the proposed approach for applications from the domain of audio processing and real-time avionics. In this paper we describe the REFLECT approach and present a number of examples and results using REFLECT's compilation and synthesis tools.

Demonstration

Publications

1. J. Vandebon, J.G.F. Coutinho, W. Luk, E. Nurvitadhi and T. Todman. "Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies". In Proc. IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2020. (pdf)
2. J.M.P. Cardoso, J. Teixeira, J. Alves, R. Nobre, P.C. Diniz, J.G.F. Coutinho and W. Luk. "Specifying Compiler Strategies for FPGA-based Systems". In Proc. IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2012. (pdf)
3. J.M.P. Cardoso, T. Carvalho, J.G.F. Coutinho, W. Luk, R. Nobre, P.C. Diniz and Z. Petrov. "LARA: An Aspect-Oriented Programming Language for Embedded Systems". In Proc. International Conference on Aspect-Oriented Software Development (AOSD), pp. 179-190, 2012. (pdf)
4. J.M.P. Cardoso et al, "New Approach to Control and Guide the Mapping of Computations to FPGAs". In Proc. Engineering of Reconfigurable Systems and Algorithms (ERSA), 2011. (pdf)