---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:43:21 12/15/2006 -- Design Name: -- Module Name: syn2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity syn7 is Port ( in1 : in STD_LOGIC_VECTOR (31 downto 0); in2 : in STD_LOGIC_VECTOR (31 downto 0); in3 : in STD_LOGIC_VECTOR (31 downto 0); in4 : in STD_LOGIC_VECTOR (31 downto 0); in5 : in STD_LOGIC_VECTOR (31 downto 0); out_1 : out STD_LOGIC_VECTOR (31 downto 0); out_2 : out STD_LOGIC_VECTOR (31 downto 0); out_3 : out STD_LOGIC_VECTOR (31 downto 0); out_4 : out STD_LOGIC_VECTOR (31 downto 0); rst : in STD_LOGIC; start : in boolean; finish : out boolean; clk : in STD_LOGIC ); end syn7; architecture rtl of syn7 is component fpadder port ( CLK : in std_logic ; FA : in std_logic_vector( 32 - 1 downto 0); FB : in std_logic_vector( 32 - 1 downto 0); Q : out std_logic_vector( 32 - 1 downto 0); start: in boolean; finish: out boolean ); end component; component fpmult port ( CLK : in std_logic ; FA : in std_logic_vector( 32 - 1 downto 0); FB : in std_logic_vector( 32 - 1 downto 0); Q : out std_logic_vector( 32 - 1 downto 0); start: in boolean; finish: out boolean ); end component; signal in1_reg : std_logic_vector (31 downto 0); signal in2_reg : std_logic_vector (31 downto 0); signal in3_reg : std_logic_vector (31 downto 0); signal in4_reg : std_logic_vector (31 downto 0); signal in5_reg : std_logic_vector (31 downto 0); signal le5 : std_logic_vector (31 downto 0); signal le6 : std_logic_vector (31 downto 0); signal le7 : std_logic_vector (31 downto 0); signal le8 : std_logic_vector (31 downto 0); signal le9 : std_logic_vector (31 downto 0); signal le10 : std_logic_vector (31 downto 0); signal le11 : std_logic_vector (31 downto 0); signal le12 : std_logic_vector (31 downto 0); signal le13 : std_logic_vector (31 downto 0); signal le14 : std_logic_vector (31 downto 0); signal le15 : std_logic_vector (31 downto 0); signal le16 : std_logic_vector (31 downto 0); signal le17 : std_logic_vector (31 downto 0); signal le18 : std_logic_vector (31 downto 0); signal le19 : std_logic_vector (31 downto 0); signal le20 : std_logic_vector (31 downto 0); signal le21 : std_logic_vector (31 downto 0); signal le22 : std_logic_vector (31 downto 0); signal le23 : std_logic_vector (31 downto 0); signal le24 : std_logic_vector (31 downto 0); signal le25 : std_logic_vector (31 downto 0); signal le26 : std_logic_vector (31 downto 0); signal le27 : std_logic_vector (31 downto 0); signal le28 : std_logic_vector (31 downto 0); signal le29 : std_logic_vector (31 downto 0); signal le30 : std_logic_vector (31 downto 0); signal le31 : std_logic_vector (31 downto 0); signal le32 : std_logic_vector (31 downto 0); signal le33 : std_logic_vector (31 downto 0); signal le34 : std_logic_vector (31 downto 0); signal le35 : std_logic_vector (31 downto 0); signal le36 : std_logic_vector (31 downto 0); signal le37 : std_logic_vector (31 downto 0); signal le38 : std_logic_vector (31 downto 0); signal le39 : std_logic_vector (31 downto 0); signal le40 : std_logic_vector (31 downto 0); signal le41 : std_logic_vector (31 downto 0); signal le42 : std_logic_vector (31 downto 0); signal le43 : std_logic_vector (31 downto 0); signal le44 : std_logic_vector (31 downto 0); signal le45 : std_logic_vector (31 downto 0); signal le46 : std_logic_vector (31 downto 0); signal le47 : std_logic_vector (31 downto 0); signal le48 : std_logic_vector (31 downto 0); signal le49 : std_logic_vector (31 downto 0); signal le50 : std_logic_vector (31 downto 0); signal le51 : std_logic_vector (31 downto 0); signal le52 : std_logic_vector (31 downto 0); signal le53 : std_logic_vector (31 downto 0); signal le54 : std_logic_vector (31 downto 0); signal reg1 : std_logic_vector (31 downto 0); signal start_reg :boolean; signal start_reg1 :boolean; signal start_reg2 :boolean; signal start_reg3 :boolean; signal start_reg4 :boolean; signal start_reg5 :boolean; signal start_reg6 :boolean; signal start_reg7 :boolean; signal start_reg8 :boolean; signal start_reg9 :boolean; signal start_reg10 :boolean; signal start_reg11 :boolean; signal start_reg12 :boolean; signal start_reg13 :boolean; signal finish5 : boolean; signal finish6 : boolean; signal finish7 : boolean; signal finish8 : boolean; signal finish9 : boolean; signal finish10 : boolean; signal finish11 : boolean; signal finish12 : boolean; signal finish13 : boolean; signal finish14 : boolean; signal finish15 : boolean; signal finish16 : boolean; signal finish17 : boolean; signal finish18 : boolean; signal finish19 : boolean; signal finish20 : boolean; signal finish21 : boolean; signal finish22 : boolean; signal finish23 : boolean; signal finish24 : boolean; signal finish25 : boolean; signal finish26 : boolean; signal finish27 : boolean; signal finish28 : boolean; signal finish29 : boolean; signal finish30 : boolean; signal finish31 : boolean; signal finish32 : boolean; signal finish33 : boolean; signal finish34 : boolean; signal finish35 : boolean; signal finish36 : boolean; signal finish37 : boolean; signal finish38 : boolean; signal finish39 : boolean; signal finish40 : boolean; signal finish41 : boolean; signal finish42 : boolean; signal finish43 : boolean; signal finish44 : boolean; signal finish45 : boolean; signal finish46 : boolean; signal finish47 : boolean; signal finish48 : boolean; signal finish49 : boolean; signal finish50 : boolean; signal finish51 : boolean; signal finish52 : boolean; signal finish53 : boolean; signal finish54 : boolean; signal temp_finish1 : boolean; signal temp_finish2 : boolean; signal temp_finish3 : boolean; signal temp_finish4 : boolean; signal temp_finish5 : boolean; signal temp_finish6 : boolean; signal temp_finish7 : boolean; begin u1 : fpadder port map ( clk => clk, FA => in1_reg, FB => in2_reg, Q => le5, start => start_reg1, finish => finish5); u2 : fpmult port map ( clk => clk, FA => in3_reg, FB => in4_reg, Q => le6, start => start_reg1, finish => finish6); u3 : fpadder port map ( clk => clk, FA => in3_reg, FB => in1_reg, Q => le7, start => start_reg1, finish => finish7); u4 : fpmult port map ( clk => clk, FA => in4_reg, FB => in5_reg, Q => le8, start => start_reg1, finish => finish8); u5 : fpadder port map ( clk => clk, FA => le5, FB => le6, Q => le9, start => start_reg2, finish => finish9); u6 : fpmult port map ( clk => clk, FA => le7, FB => le8, Q => le10, start => start_reg2, finish => finish10); u7 : fpadder port map ( clk => clk, FA => le9, FB => le10, Q => le11, start => start_reg2, finish => finish11); u8 : fpmult port map ( clk => clk, FA => le9, FB => le10, Q => le12, start => start_reg2, finish => finish12); u9 : fpadder port map ( clk => clk, FA => le5, FB => le6, Q => le13, start => start_reg3, finish => finish13); u10 : fpmult port map ( clk => clk, FA => le7, FB => le8, Q => le14, start => start_reg3, finish => finish14); u11 : fpadder port map ( clk => clk, FA => le13, FB => le14, Q => le15, start => start_reg3, finish => finish15); u12 : fpmult port map ( clk => clk, FA => le13, FB => le9, Q => le16, start => start_reg3, finish => finish16); u13 : fpadder port map ( clk => clk, FA => le13, FB => le14, Q => le17, start => start_reg4, finish => finish17); u14 : fpmult port map ( clk => clk, FA => le10, FB => le14, Q => le18, start => start_reg4, finish => finish18); u15 : fpadder port map ( clk => clk, FA => le15, FB => le17, Q => le19, start => start_reg4, finish => finish19); u16 : fpmult port map ( clk => clk, FA => le18, FB => le15, Q => le20, start => start_reg4, finish => finish20); u17 : fpadder port map ( clk => clk, FA => le12, FB => le18, Q => le21, start => start_reg5, finish => finish21); u18 : fpmult port map ( clk => clk, FA => le20, FB => le19, Q => le22, start => start_reg5, finish => finish22); u19 : fpadder port map ( clk => clk, FA => le20, FB => le21, Q => le23, start => start_reg5, finish => finish23); u20 : fpmult port map ( clk => clk, FA => le19, FB => le21, Q => le24, start => start_reg5, finish => finish24); u21 : fpadder port map ( clk => clk, FA => le23, FB => le22, Q => le25, start => start_reg6, finish => finish25); u22 : fpmult port map ( clk => clk, FA => le51, FB => le52, Q => le26, start => start_reg6, finish => finish26); u23 : fpadder port map ( clk => clk, FA => le54, FB => le52, Q => le27, start => start_reg6, finish => finish27); u24 : fpmult port map ( clk => clk, FA => le54, FB => le53, Q => le28, start => start_reg6, finish => finish28); u25 : fpadder port map ( clk => clk, FA => le26, FB => le27, Q => le29, start => start_reg7, finish => finish29); u26 : fpmult port map ( clk => clk, FA => le26, FB => le28, Q => le30, start => start_reg7, finish => finish30); u27 : fpadder port map ( clk => clk, FA => le28, FB => le27, Q => le31, start => start_reg7, finish => finish31); u28 : fpmult port map ( clk => clk, FA => le26, FB => le28, Q => le32, start => start_reg7, finish => finish32); u29 : fpadder port map ( clk => clk, FA => le27, FB => le28, Q => le33, start => start_reg8, finish => finish33); u30 : fpmult port map ( clk => clk, FA => le30, FB => le32, Q => le34, start => start_reg8, finish => finish34); u31 : fpadder port map ( clk => clk, FA => le31, FB => le29, Q => le35, start => start_reg8, finish => finish35); u32 : fpmult port map ( clk => clk, FA => le33, FB => le31, Q => le36, start => start_reg8, finish => finish36); u33 : fpadder port map ( clk => clk, FA => le33, FB => le32, Q => le37, start => start_reg9, finish => finish37); u34 : fpmult port map ( clk => clk, FA => le35, FB => le34, Q => le38, start => start_reg9, finish => finish38); u35 : fpadder port map ( clk => clk, FA => le34, FB => le37, Q => le39, start => start_reg9, finish => finish39); u36 : fpmult port map ( clk => clk, FA => le36, FB => le35, Q => le40, start => start_reg9, finish => finish40); u37 : fpadder port map ( clk => clk, FA => le37, FB => le36, Q => le41, start => start_reg10, finish => finish41); u38 : fpmult port map ( clk => clk, FA => le11, FB => le16, Q => le42, start => start_reg10, finish => finish42); u39 : fpadder port map ( clk => clk, FA => le42, FB => le19, Q => le43, start => start_reg10, finish => finish43); u40 : fpmult port map ( clk => clk, FA => le42, FB => le21, Q => le44, start => start_reg10, finish => finish44); u41 : fpadder port map ( clk => clk, FA => le22, FB => le43, Q => le45, start => start_reg11, finish => finish45); u42 : fpmult port map ( clk => clk, FA => le43, FB => le24, Q => le46, start => start_reg11, finish => finish46); u43 : fpadder port map ( clk => clk, FA => le24, FB => le44, Q => le47, start => start_reg11, finish => finish47); u44 : fpmult port map ( clk => clk, FA => le45, FB => le46, Q => le48, start => start_reg11, finish => finish48); u45 : fpadder port map ( clk => clk, FA => le47, FB => le45, Q => le49, start => start_reg12, finish => finish49); u46 : fpmult port map ( clk => clk, FA => le25, FB => le45, Q => le50, start => start_reg12, finish => finish50); u47 : fpadder port map ( clk => clk, FA => le48, FB => le50, Q => le51, start => start_reg12, finish => finish51); u48 : fpmult port map ( clk => clk, FA => le49, FB => le50, Q => le52, start => start_reg12, finish => finish52); u49 : fpadder port map ( clk => clk, FA => le48, FB => le50, Q => le53, start => start_reg13, finish => finish53); u50 : fpmult port map ( clk => clk, FA => le49, FB => le50, Q => le54, start => start_reg13, finish => finish54); process(clk,rst) begin if (clk'event and clk ='1')then start_reg <= start; start_reg1 <= start_reg; start_reg2 <= start_reg; start_reg3 <= start_reg; start_reg4 <= start_reg; start_reg5 <= start_reg; start_reg6 <= start_reg; start_reg7 <= start_reg; start_reg8 <= start_reg; start_reg9 <= start_reg; start_reg10 <= start_reg; start_reg11 <= start_reg; start_reg12 <= start_reg; start_reg13<= start_reg; in1_reg <= in1; in2_reg <= in2; in3_reg <= in3; in4_reg <= in4; in5_reg <= in5; out_1 <= le38; out_2 <= le39; out_3 <= le40; out_4 <= le41; temp_finish1 <= finish5 and finish6 and finish7 and finish8 and finish9 and finish10 and finish11; temp_finish2 <= finish12 and finish13 and finish14 and finish15 and finish16 and finish17 and finish18; temp_finish3 <= finish19 and finish20 and finish21 and finish22 and finish23 and finish24 and finish25; temp_finish4 <= finish26 and finish27 and finish28 and finish29 and finish30 and finish31 and finish32; temp_finish5 <= finish33 and finish34 and finish35 and finish36 and finish37 and finish38 and finish39; temp_finish6 <= finish40 and finish41 and finish42 and finish43 and finish44 and finish45 and finish46; temp_finish7 <= finish47 and finish48 and finish49 and finish50 and finish51 and finish52 and finish53 and finish54; finish <= temp_finish1 and temp_finish2 and temp_finish3 and temp_finish4 and temp_finish5 and temp_finish6 and temp_finish7; end if; end process; end rtl;