---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:43:21 12/15/2006 -- Design Name: -- Module Name: mm3 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mm3 is Port ( ina1 : in STD_LOGIC_VECTOR (31 downto 0); ina2 : in STD_LOGIC_VECTOR (31 downto 0); ina3 : in STD_LOGIC_VECTOR (31 downto 0); inb1 : in STD_LOGIC_VECTOR (31 downto 0); inb2 : in STD_LOGIC_VECTOR (31 downto 0); inb3 : in STD_LOGIC_VECTOR (31 downto 0); output : out STD_LOGIC_VECTOR (31 downto 0); rst : in STD_LOGIC; start : in boolean; finish : out boolean; clk : in STD_LOGIC ); end mm3; architecture rtl of mm3 is component fpadder port ( CLK : in std_logic ; FA : in std_logic_vector( 32 - 1 downto 0); FB : in std_logic_vector( 32 - 1 downto 0); Q : out std_logic_vector( 32 - 1 downto 0); start: in boolean; finish: out boolean ); end component; component fpmult port ( CLK : in std_logic ; FA : in std_logic_vector( 32 - 1 downto 0); FB : in std_logic_vector( 32 - 1 downto 0); Q : out std_logic_vector( 32 - 1 downto 0); start: in boolean; finish: out boolean ); end component; signal ina1_reg : std_logic_vector (31 downto 0); signal ina2_reg : std_logic_vector (31 downto 0); signal ina3_reg : std_logic_vector (31 downto 0); signal inb1_reg : std_logic_vector (31 downto 0); signal inb2_reg : std_logic_vector (31 downto 0); signal inb3_reg : std_logic_vector (31 downto 0); signal x1 : std_logic_vector (31 downto 0); signal x2 : std_logic_vector (31 downto 0); signal x3 : std_logic_vector (31 downto 0); signal add4 : std_logic_vector (31 downto 0); signal add5 : std_logic_vector (31 downto 0); signal start_reg : boolean; signal finish1 : boolean; signal finish2 : boolean; signal finish3 : boolean; signal finish4 : boolean; signal finish5 : boolean; signal x3_reg1 : std_logic_vector (31 downto 0); signal x3_reg2 : std_logic_vector (31 downto 0); signal x3_reg3 : std_logic_vector (31 downto 0); signal x3_reg4 : std_logic_vector (31 downto 0); signal x3_reg5 : std_logic_vector (31 downto 0); signal x3_reg6 : std_logic_vector (31 downto 0); begin u_x1 : fpmult port map ( clk => clk, FA => ina1_reg, FB => inb1_reg, Q => x1, start => start_reg, finish => finish1); u_x2 : fpmult port map ( clk => clk, FA => ina2_reg, FB => inb2_reg, Q => x2, start => start_reg, finish => finish2); u_x3 : fpmult port map ( clk => clk, FA => ina3_reg, FB => inb3_reg, Q => x3, start => start_reg, finish => finish3); u_a4 : fpadder port map ( clk => clk, FA => x1, FB => x2, Q => add4 , start => start_reg, finish => finish4); u_a5 : fpadder port map ( clk => clk, FA => add4, FB => x3_reg6, Q => add5 , start => start_reg, finish => finish5); process(clk,rst) begin if (clk'event and clk ='1')then ina1_reg <= ina1; ina2_reg <= ina2; ina3_reg <= ina3; inb1_reg <= inb1; inb2_reg <= inb2; inb3_reg <= inb3; x3_reg1 <= x3; x3_reg2 <= x3_reg1; x3_reg3 <= x3_reg2; x3_reg4 <= x3_reg3; x3_reg5 <= x3_reg4; x3_reg6 <= x3_reg5; output <= add5; start_reg <= start; finish <= finish1 and finish2 and finish3 and finish4 and finish5; end if; end process; end rtl;