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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:43:21 12/15/2006 
-- Design Name: 
-- Module Name:    dscg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dscg is
    Port ( 
		one : in  STD_LOGIC_VECTOR (31 downto 0);
		cos : in  STD_LOGIC_VECTOR (31 downto 0);
		s1 : in  STD_LOGIC_VECTOR (31 downto 0);
		s2 : in  STD_LOGIC_VECTOR (31 downto 0);

		s1out : out  STD_LOGIC_VECTOR (31 downto 0);
		s2out : out  STD_LOGIC_VECTOR (31 downto 0);

		rst : in STD_LOGIC;
		start : in boolean;
		finish : out boolean;
		clk : in  STD_LOGIC
);
end dscg;



architecture rtl of dscg is

component fpadder
port ( 
      CLK : in std_logic ;
      FA  : in std_logic_vector( 32 - 1 downto 0);
      FB  : in std_logic_vector( 32 - 1 downto 0);
      Q   : out std_logic_vector( 32 - 1 downto 0);
	start: in boolean;
	finish: out boolean
     );
end component;
component fpmult
port ( 
      CLK : in std_logic ;
      FA  : in std_logic_vector( 32 - 1 downto 0);
      FB  : in std_logic_vector( 32 - 1 downto 0);
      Q   : out std_logic_vector( 32 - 1 downto 0);
	start: in boolean;
	finish: out boolean
     );
end component;


signal cos_reg : std_logic_vector (31 downto 0); 
signal one_reg : std_logic_vector (31 downto 0); 
signal s1_reg : std_logic_vector (31 downto 0);
signal s2_reg : std_logic_vector (31 downto 0);

signal start_reg : boolean;
signal finish1 : boolean;
signal finish2 : boolean;
signal finish3 : boolean;
signal finish4 : boolean;
signal finish5 : boolean;
signal finish6 : boolean;
signal finish7 : boolean;
signal finish8 : boolean;

-- for component x1
signal x2 : std_logic_vector (31 downto 0); 
signal x3 : std_logic_vector (31 downto 0); 
signal x6 : std_logic_vector (31 downto 0);
signal x7 : std_logic_vector (31 downto 0);

signal add1 : std_logic_vector (31 downto 0);
signal add4 : std_logic_vector (31 downto 0);
signal sub5 : std_logic_vector (31 downto 0);
signal add8 : std_logic_vector (31 downto 0);

signal x3_reg1 : std_logic_vector (31 downto 0); 
signal x3_reg2 : std_logic_vector (31 downto 0); 
signal x3_reg3 : std_logic_vector (31 downto 0); 
signal x3_reg4 : std_logic_vector (31 downto 0); 
signal x3_reg5 : std_logic_vector (31 downto 0); 
signal x3_reg6 : std_logic_vector (31 downto 0); 

signal x7_reg1 : std_logic_vector (31 downto 0); 
signal x7_reg2 : std_logic_vector (31 downto 0); 
signal x7_reg3 : std_logic_vector (31 downto 0); 
signal x7_reg4 : std_logic_vector (31 downto 0); 
signal x7_reg5 : std_logic_vector (31 downto 0); 
signal x7_reg6 : std_logic_vector (31 downto 0); 

begin
	u_a1 : fpadder port map (
		clk => clk,
		FA => cos_reg,
		FB => one_reg,
		Q => add1 ,
		start => start_reg,
		finish => finish1);

	u_x2 : fpmult port map (
		clk => clk,
		FA => add1,
		FB => s2_reg,
		Q => x2,
		start => start_reg,
		finish => finish2);

	u_x3 : fpmult port map (
		clk => clk,
		FA => cos_reg,
		FB => s1_reg,
		Q => x3,
		start => start_reg,
		finish => finish3);

	u_a4 : fpadder port map (
		clk => clk,
		FA => x2,
		FB => x3_reg6,
		Q => add4 ,
		start => start_reg,
		finish => finish4);

	u_a5 : fpadder port map (
		clk => clk,
		FA => one_reg,
		FB => cos_reg,
		Q => sub5,
		start => start_reg,
		finish => finish5);

	u_x6 : fpmult port map (
		clk => clk,
		FA => sub5,
		FB => s1_reg,
		Q => x6,
		start => start_reg,
		finish => finish6);

	u_x7 : fpmult port map (
		clk => clk,
		FA => cos_reg,
		FB => s2_reg,
		Q => x7,
		start => start_reg,
		finish => finish7);

	u_a8 : fpadder port map (
		clk => clk,
		FA => x6,
		FB => x7_reg6,
		Q => add8,
		start => start_reg,
		finish => finish8);


	process(clk,rst)
	begin
		if (clk'event and clk ='1')then
					cos_reg <= cos;
					one_reg <= one;
					s1_reg <= s1;
					s2_reg <= s2;


					x3_reg1 <= x3;
					x3_reg2 <= x3_reg1;
					x3_reg3 <= x3_reg2;
					x3_reg4 <= x3_reg3;
					x3_reg5 <= x3_reg4;
					x3_reg6 <= x3_reg5;

					x7_reg1 <= x7;
					x7_reg2 <= x7_reg1;
					x7_reg3 <= x7_reg2;
					x7_reg4 <= x7_reg3;
					x7_reg5 <= x7_reg4;
					x7_reg6 <= x7_reg5;

					s1out <= add4;
					s2out <= add8;			


					start_reg <= start;

					finish <= finish1 and finish2 and finish3 and finish4 and finish5 and finish6 and finish7 and finish8;
		end if;
	end process;

end rtl;