---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:43:21 12/15/2006 -- Design Name: -- Module Name: ode - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ode is Port ( h : in STD_LOGIC_VECTOR (63 downto 0); half : in STD_LOGIC_VECTOR (63 downto 0); ypi : in STD_LOGIC_VECTOR (63 downto 0); tpi: in STD_LOGIC_VECTOR (63 downto 0); tpiout : out STD_LOGIC_VECTOR (63 downto 0); ypiout : out STD_LOGIC_VECTOR (63 downto 0); sel : in boolean; rst : in STD_LOGIC; start : in boolean; finish : out boolean; clk : in STD_LOGIC ); end ode; architecture rtl of ode is component fpadder2 port ( CLK : in std_logic ; FA : in std_logic_vector( 63 downto 0); FB : in std_logic_vector( 63 downto 0); Q : out std_logic_vector( 63 downto 0); start: in boolean; finish: out boolean ); end component; component fpmult2 port ( CLK : in std_logic ; FA : in std_logic_vector( 63 downto 0); FB : in std_logic_vector( 63 downto 0); Q : out std_logic_vector( 63 downto 0); start: in boolean; finish: out boolean ); end component; signal h_reg : std_logic_vector (63 downto 0); signal half_reg : std_logic_vector (63 downto 0); signal ypi_reg : std_logic_vector (63 downto 0); signal tpi_reg : std_logic_vector (63 downto 0); signal x1 : std_logic_vector (63 downto 0); signal sub2 : std_logic_vector (63 downto 0); signal x3 : std_logic_vector (63 downto 0); signal add4 : std_logic_vector (63 downto 0); signal add5 : std_logic_vector (63 downto 0); signal start_reg : boolean; signal finish1 : boolean; signal finish2 : boolean; signal finish3 : boolean; signal finish4 : boolean; signal finish5 : boolean; signal treg1 : std_logic_vector (63 downto 0); signal treg2 : std_logic_vector (63 downto 0); signal treg3 : std_logic_vector (63 downto 0); signal treg4 : std_logic_vector (63 downto 0); signal treg5 : std_logic_vector (63 downto 0); signal treg6 : std_logic_vector (63 downto 0); signal treg7 : std_logic_vector (63 downto 0); signal treg8 : std_logic_vector (63 downto 0); signal treg9 : std_logic_vector (63 downto 0); signal treg10 : std_logic_vector (63 downto 0); signal treg11 : std_logic_vector (63 downto 0); signal treg12 : std_logic_vector (63 downto 0); signal ypireg1 : std_logic_vector (63 downto 0); signal ypireg2 : std_logic_vector (63 downto 0); signal ypireg3 : std_logic_vector (63 downto 0); signal ypireg4 : std_logic_vector (63 downto 0); signal ypireg5 : std_logic_vector (63 downto 0); signal ypireg6 : std_logic_vector (63 downto 0); signal ypireg7 : std_logic_vector (63 downto 0); signal ypireg8 : std_logic_vector (63 downto 0); signal ypireg9 : std_logic_vector (63 downto 0); signal ypireg10 : std_logic_vector (63 downto 0); signal ypireg11 : std_logic_vector (63 downto 0); signal ypireg12 : std_logic_vector (63 downto 0); begin u_x1 : fpmult2 port map ( clk => clk, FA => h_reg, FB => half_reg, Q => x1 , start => start_reg, finish => finish1); u_sub2 : fpadder2 port map ( clk => clk, FA => tpi_reg, FB => ypi_reg, Q => sub2 , start => start_reg, finish => finish2); u_x3 : fpmult2 port map ( clk => clk, FA => x1, FB => sub2, Q => x3 , start => start_reg, finish => finish3); u_add4 : fpadder2 port map ( clk => clk, FA => ypireg12, FB => x3, Q => add4, start => start_reg, finish => finish4); u_add5 : fpadder2 port map ( clk => clk, FA => h_reg, FB => tpi_reg, Q => add5, start => start_reg, finish => finish5); process(clk,rst) begin if (clk'event and clk ='1')then h_reg <= h; half_reg <= half; if (sel) then ypi_reg <= ypi; else ypi_reg <= add4; end if; if (sel) then tpi_reg <= tpi; else tpi_reg <= treg12; end if; ypireg1 <= ypi_reg; ypireg2 <= ypireg1; ypireg3 <= ypireg2; ypireg4 <= ypireg3; ypireg5 <= ypireg4; ypireg6 <= ypireg5; ypireg7 <= ypireg6; ypireg8 <= ypireg7; ypireg9 <= ypireg8; ypireg10 <= ypireg9; ypireg11 <= ypireg10; ypireg12 <= ypireg11; treg1 <= add5; treg2 <= treg1; treg3 <= treg2; treg4 <= treg3; treg5 <= treg4; treg6 <= treg5; treg7 <= treg6; treg8 <= treg7; treg9 <= treg8; treg10 <= treg9; treg11 <= treg10; treg12 <= treg11; ypiout <= add4; tpiout <= treg12; start_reg <= start; finish <= finish1 and finish2 and finish3 and finish4 and finish5; end if; end process; end rtl;