---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:43:21 12/15/2006 -- Design Name: -- Module Name: butterfly - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity butterfly is Port ( re_w : in STD_LOGIC_VECTOR (63 downto 0); re_x : in STD_LOGIC_VECTOR (63 downto 0); re_y : in STD_LOGIC_VECTOR (63 downto 0); im_w : in STD_LOGIC_VECTOR (63 downto 0); im_x : in STD_LOGIC_VECTOR (63 downto 0); im_y : in STD_LOGIC_VECTOR (63 downto 0); re_z : out STD_LOGIC_VECTOR (63 downto 0); im_z : out STD_LOGIC_VECTOR (63 downto 0); rst : in STD_LOGIC; start : in boolean; finish : out boolean; clk : in STD_LOGIC ); end butterfly; architecture rtl of butterfly is component fpadder2 port ( CLK : in std_logic ; FA : in std_logic_vector( 63 downto 0); FB : in std_logic_vector( 63 downto 0); Q : out std_logic_vector( 63 downto 0); start: in boolean; finish: out boolean ); end component; component fpmult2 port ( CLK : in std_logic ; FA : in std_logic_vector( 63 downto 0); FB : in std_logic_vector( 63 downto 0); Q : out std_logic_vector( 63 downto 0); start: in boolean; finish: out boolean ); end component; signal x1 : std_logic_vector (63 downto 0); signal x2 : std_logic_vector (63 downto 0); signal x3 : std_logic_vector (63 downto 0); signal x4 : std_logic_vector (63 downto 0); signal a1 : std_logic_vector (63 downto 0); signal a2 : std_logic_vector (63 downto 0); signal a3 : std_logic_vector (63 downto 0); signal a4 : std_logic_vector (63 downto 0); signal start_reg : boolean; signal finish1 : boolean; signal finish2 : boolean; signal finish3 : boolean; signal finish4 : boolean; signal finish5 : boolean; signal finish6 : boolean; signal finish7 : boolean; signal finish8 : boolean; signal re_w_reg : std_logic_vector (63 downto 0); signal re_x_reg : std_logic_vector (63 downto 0); signal re_y_reg : std_logic_vector (63 downto 0); signal im_w_reg : std_logic_vector (63 downto 0); signal im_x_reg : std_logic_vector (63 downto 0); signal im_y_reg : std_logic_vector (63 downto 0); signal re_y_reg1 : std_logic_vector (63 downto 0); signal re_y_reg2 : std_logic_vector (63 downto 0); signal re_y_reg3 : std_logic_vector (63 downto 0); signal re_y_reg4 : std_logic_vector (63 downto 0); signal re_y_reg5 : std_logic_vector (63 downto 0); signal re_y_reg6 : std_logic_vector (63 downto 0); signal im_y_reg1 : std_logic_vector (63 downto 0); signal im_y_reg2 : std_logic_vector (63 downto 0); signal im_y_reg3 : std_logic_vector (63 downto 0); signal im_y_reg4 : std_logic_vector (63 downto 0); signal im_y_reg5 : std_logic_vector (63 downto 0); signal im_y_reg6 : std_logic_vector (63 downto 0); begin u_x1 : fpmult2 port map ( clk => clk, FA => re_x_reg, FB => re_w_reg, Q => x1 , start => start_reg, finish => finish1); u_x2 : fpmult2 port map ( clk => clk, FA => im_x_reg, FB => im_w_reg, Q => x2 , start => start_reg, finish => finish2); u_x3 : fpmult2 port map ( clk => clk, FA => re_x_reg, FB => im_w_reg, Q => x3 , start => start_reg, finish => finish3); u_x4 : fpmult2 port map ( clk => clk, FA => im_x_reg, FB => re_w_reg, Q => x4 , start => start_reg, finish => finish4); u_a1 : fpadder2 port map ( clk => clk, FA => x1, FB => x2, Q => a1 , start => start_reg, finish => finish5); u_a2 : fpadder2 port map ( clk => clk, FA => x3, FB => x4, Q => a2 , start => start_reg, finish => finish6); u_a3 : fpadder2 port map ( clk => clk, FA => a1, FB => re_y_reg6, Q => a3 , start => start_reg, finish => finish7); u_a4 : fpadder2 port map ( clk => clk, FA => a2, FB => im_y_reg6, Q => a4 , start => start_reg, finish => finish8); process(clk,rst) begin if (clk'event and clk ='1')then start_reg <= start; re_w_reg <= re_w; re_x_reg <= re_x; re_y_reg <= re_y; im_w_reg <= im_w; im_x_reg <= im_x; im_y_reg <= im_y; re_y_reg1 <= re_y_reg; re_y_reg2 <= re_y_reg1; re_y_reg3 <= re_y_reg2; re_y_reg4 <= re_y_reg3; re_y_reg5 <= re_y_reg4; re_y_reg6 <= re_y_reg5; im_y_reg1 <= im_y_reg; im_y_reg2 <= im_y_reg1; im_y_reg3 <= im_y_reg2; im_y_reg4 <= im_y_reg3; im_y_reg5 <= im_y_reg4; im_y_reg6 <= im_y_reg5; re_z <= a3; im_z <= a4; finish <= finish1 and finish2 and finish3 and finish4 and finish5 and finish6 and finish7 and finish8; end if; end process; end rtl;